New 
Physical design Staff Application engineer
 Synopsys | |
$112000-$168000
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 United States, Oregon, Hillsboro | |
 Oct 05, 2026 | |
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We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the trenches of physical design, working on chips that actually tape out and ship in products people use. The difference between a design that closes timing and one that burns three months of schedule is something you can see coming in the floorplan stage, and you are the kind of engineer who speaks up before it becomes a crisis. You know Fusion Compiler or ICC2 well enough that you can debug a routing congestion issue at 9pm on a customer call and walk out with a plan that actually works.Scripting is not a side skill for you, it is how you think. You build flows in TCL and Python that do not just automate tasks but make design decisions smarter and more predictable. When someone says "the tool is doing something weird," you are the one who digs into the log files, finds the root cause, and writes the fix that prevents it from happening again.You are comfortable working directly with customers, not just handing off a deck but sitting in the room, understanding their constraints, and building solutions that fit their reality. At Synopsys, you will work on the hardest physical design problems in the industry, on the most advanced nodes, with customers who are building the chips that power everything.What You'll Be DoingSupport customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools including Fusion Compiler, helping them hit PPA targets under real schedule and resource constraintsDevelop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flowDebug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraintsBuild and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not generic best practices but solutions that fit their specific contextContribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve implementation challenges that traditional methods struggle withCollaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature enhancements that make it into the next releaseTravel to customer sites as needed to provide onsite support, training, and design reviews, often under tight deadlines and high-stakes tape-out pressureThe Impact You Will HaveEnable customers to achieve timing closure and tape-out success on advanced-node designs that define next-generation AI, mobile, and datacenter productsBuild automation and methodology improvements that get reused across multiple customer engagements, multiplying your impact across dozens of designsShape the roadmap of Synopsys physical design tools by feeding real customer challenges directly into R&D, influencing features that thousands of engineers will useReduce design cycle time and improve PPA outcomes for customers working at the cutting edge of semiconductor technology, where every percentage point of performance or power mattersMentor field teams and customers on advanced physical design techniques, raising the bar for how complex designs get implemented across the industryHelp drive adoption of AI-driven optimization methodologies that change how physical design gets done, not just incrementally but fundamentallyStrengthen customer relationships by being the engineer they call when a design is stuck and they need someone who can actually solve the problem, not just escalate itWhat You'll NeedBachelor's degree in electrical engineering or a related field with 5+ years of hands-on ASIC physical design experience, or a master's degree with 3+ years of experienceProficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus, you have used these tools on real tapeouts, not just in trainingStrong scripting and automation skills using TCL, Python, or Perl to build flows, analyze data, and solve problems that do not have a button in the GUISolid understanding of advanced-node design challenges at 7nm and below, including FinFET effects, multi-patterning, electromigration, and the tradeoffs that come with eachExperience with logical and physical synthesis flows, and familiarity with AI-driven optimization methodologies is a strong plusExcellent communication and presentation skills, you can explain a complex timing closure strategy to a customer engineering team and a high-level roadblock to their management in the same meetingWillingness to travel to customer sites as needed, sometimes on short notice, to provide onsite support during critical design phasesWho You AreYou can walk into a customer meeting with incomplete information, ask the right questions, and leave with a clear plan that the team actually believes inWhen a design is failing timing by 500ps and the customer is two weeks from tape-out, you do not panic, you methodically work the problem until you find the path to closureYou write scripts that other engineers can actually read and modify, not just code that works but code that scales across a teamYou push back when a methodology recommendation does not fit the customer's reality, even if it means more work to find the right answerYou can explain a complex physical design tradeoff to a VP in two sentences without losing the nuance, and then turn around and debug a TCL flow issue with an engineerYou treat customer problems like your own, not because you have to but because you care about the outcome and you know your work directly affects whether their chip succeeds or failsThe Team You'll Be Part OfYour recruiter will share more about the team structure and mission during the interview process.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S. Apply Now | |