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Job Family Description
Support a balance of sustaining, optimization, and qualification of wafer fabrication processes, including etch, and deposition and photolithography. These processes are applied to both existing and new technology generations of Nokia's InP based Photonic Integrated Circuits (PICs).
Assist process engineers in the development of wafer process recipes, operational procedures, and provide other support needed to qualify new tools needed for the release of an additional PIC wafer manufacturing site. Collect, interpret, and respond to wafer fab statistical process control (SPC) data in the etch, deposition, and photolithography modules. Support the wafer fab engineering and operations teams to develop, control and optimize wafer fabrication processes Work in teams to scale PIC wafer fabrication processes to larger wafer sizes, while meeting key objectives for PIC yield, uniformity, and end-of-line parametric performance. Troubleshoot wafer fabrication process problems to enable a smooth flow of production and development wafers in the fab. Support engineering process and tool owners in resolving fab process or equipment problems at 2 bay area manufacturing sites. Assist process engineers in utilizing metrology equipment and test structures to maintain process control across wafer fab process modules, improve production yield and enable and guide new process development.
JMP, DOE, SPC and similar data analysis tools and their application to semiconductor manufacturing Working knowledge of semiconductor fabrication processes, and expertise in etch, deposition, photolithography and related processes. Strong initiative and communication skills. Experience with semiconductor process development, sustaining, new process introduction, and ramp to volume. Experience supporting a 24x7 fab operations team, writing and training of fab procedures, root cause analysis and problem resolution.
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