Principal Design Verification Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• Develop the architecture for a functionalverificationenvironment, including reference models and bus-functional monitors and drivers.
• Work closely with architects/RTL engineers to bring-up a newarchitecture/micro-architectureon theverificationenvironment.
• Develop testbench components in SystemVerilog, UVM, C, and C++. Write tests in SystemVerilog, UVM, C, C++, python to test various logical features in ASIC and SOC design blocks.
• Debug failures in tests and root cause issues with test environment and design.
• Write averificationtest plan using random techniques and coverage analysis, and work with designers to ensure it is complete.
• Develop tests and tune the environment to achieve coverage goals.
• Own and debug failures in simulation to root cause problems
• Architecting, developing, and maintaining tools to streamline the design of state-of-the-art multicore SoCs.
• Analysis/closure of code and functional coverage.

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
• Experience with functional verification techniques.
• Strong understanding of digital design principles and methodologies.
• Hands-on experience on using Verilog, System Verilog and C++
• Understanding of Ethernet networking.
• Excellent problem-solving and debugging skills.
• Effective communication and collaboration skills.
• Ability to work in a fast-paced, dynamic environment.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.