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ASIC Design Verification Engineer

Spectraforce Technologies
United States, California, San Diego
Jan 21, 2026
Job Title: ASIC Design Verification Engineer

Location: San Diego, CA 92121

Duration : 12 Months

Work Schedule: Monday-Friday, 8:30 AM - 5:00 PM PST


Role Overview

Join Design Verification team to verify high-speed mixed-signal IPs used in cutting-edge products for 5G, AI/ML, compute, IoT, and automotive applications. The team owns the complete design verification lifecycle, from system-level concept through tape-out and post-silicon validation.

Key Responsibilities

  • Define pre-silicon and post-silicon test plans based on design specifications and industry standards
  • Work closely with design teams to ensure complete verification coverage and design quality
  • Architect and develop verification environments using SystemVerilog and UVM
  • Perform analog/mixed-signal simulation, low-power verification, formal verification, and gate-level simulation
  • Develop SVA assertions, test cases, and coverage models; drive coverage closure
  • Debug complex functional and performance issues across verification stages
  • Collaborate with digital design, analog circuit design, modeling, controller, subsystem, and SoC integration teams
  • Support PHY-level verification, subsystem/SoC integration, and post-silicon validation



Required Skills & Qualifications

  • Strong knowledge of SystemVerilog and UVM verification methodology
  • Hands-on experience with ASIC verification tools such as:
  • Synopsys VCS
  • Cadence Xcelium (NCsim)
  • ModelSim / Questa
  • Formal tools: VC Formal, JasperGold, 0-In, or equivalent
  • Experience verifying high-speed interfaces and mixed-signal IPs
  • Proficiency in assertion-based verification (SVA)
  • Experience with scripting languages such as Python or Perl



Preferred Qualifications

  • Experience with low-power design verification
  • Experience with formal verification and gate-level simulation
  • From-scratch VIP development experience for SerDes controller PHYs
  • Strong understanding of mixed-signal IP verification
  • Protocol & Technology Experience
  • High-speed interfaces and IPs including:
  • PCIe, USB, MIPI, LPDDR, DDR, CXL, C2C, D2D, UFS
  • PLL, DAC, ADC, Sensors


Education

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field


Experience

  • 5+ years of ASIC design verification or related experience


Physical & Other Requirements

  • No lifting, pushing, pulling, or driving requirements

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