New

Principal System Engineer

Marvell Semiconductor, Inc.
paid time off, flex time, 401(k)
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
May 02, 2025
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell post silicon validation group designs and develops test platforms for validating multi-core Arm-based Network processors used in many communication infrastructure applications such as 5G base stations and cloud computing platforms. The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SerDes and DDR interfaces on the processor. The SerDes interface use NRZ and PAM4 signaling for Ethernet, CPRI, JESD, and PCIe interfaces. DRAM interfaces include LPDDR5, DDR4/5 memory modules. Characterization engineers are responsible for developing test platforms used and automated test suites to characterize the analog interfaces over process voltage and temperature (PVT) extremes to determine silicon viability for volume production. The ideal candidate should have a strong background in characterization and design of SERDES IP with special consideration for direct experience in the processors industry. The ideal candidate would have in depth knowledge of the SERDES architecture and measurement methods, especially for PCIe and Ethernet interfaces. The candidate must have in depth knowledge of the instrumentation necessary for testing the SERDES IP and a strong commitment to ensuring characterization of such IP for extremely high-volume production. In this position, the candidate will be responsible for leading and building a strong team for SERDES device validation and SERDES IP characterization. The candidate will be responsible for the development and implementation of the characterization and support strategy for the SERDES IP included in almost all products of the Business Group. What You Can Expect Marvell is seeking an experienced Senior Principal SERDES signal integrity engineer in the validation and applications engineering team for SERDES IP in the Custom Compute and Storage Business Group. Own the electrical characterization/compliance of SERDES IP for PCIe and Networking (Ethernet). Develop and implement test plans for SERDES characterization. Develop methods for automated electrical characterization (validation) of the interfaces. Develop standard test methods and regression tests for the validation of the IPs. Mentor junior engineers in the SERDES validation and applications engineering teams for the BU. Provide applications engineering support to major customers. Develop the technical skillset in the team to handle complex SERDES debugging issues. Represent Marvell's interest at the standards committees and be an active contributor on these committees. Ensure that our planning for future SERDES IP is well addressed from an equipment and training perspective. Support high-speed board design, debug and board extraction, definition and characterization for the SERDES devices as well as collaborate with the internal tools engineering team to design the test infrastructure. Must have proven ability to work with executive management to develop and implement long term solutions impacting the success of the business group. What We're Looking For Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience. In depth knowledge of SERDES interface using NRZ and PAM4 signaling for Ethernet and PCIe interfaces, knowledge of relevant Ethernet standards (e.g., 10GbE, 100GbE, 400GbE)is a plus. In depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer etc.). Deep understanding of high-speed electrical signaling principles, differential signaling and mixed-signal designs. Experience in Python programming language for automation framework development, as well as mathematical programing such as Matlab. Critical thinking and problem-solving attitude and ownership of the group's results. Knowledge in SERDES modeling techniques Experience scripting languages such as Unix shell, Python, Perl or similar Working knowledge of board design; able to read board schematics and board layout is a plus Strong analytical, problem-solving and communication skills Expected Base Pay Range (USD) 143,200 - 214,500, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. #LI-MM1