Design Verification (DV) Engineer

Cisco Systems, Inc.
United States, California, San Jose
170 W Tasman Dr (Show on map)
Jun 11, 2025
The application window is expected to close on: 6/30/2025 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact You will work with front-end RTL Design and Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and Software teams as part of ASIC development to build a flawless handshake between hardware and software functionalities and qualify use-case requirements. You'll also have the opportunity to work with systems-testing teams during post-silicon validation efforts to bring-up, debug and qualify the ASIC in deployment-mode applications You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of the largest and most sophisticated of its kind in the industry Use the microarchitecture and define the verification plan and be responsible for the entire verification process Develop the verification environment, including crafting and implementing test plans, and perform any vital debugging You will take part in the development of simulation models, test plan, code or functional coverage, multi-chip/system simulation, and performance analysis Minimum Qualifications Bachelors of Science Electrical Engineering, Computer Science or related degree with 4+ years of design verification experience or Masters degree in Electrical Engineering, Computer Science or related degree with 2+ years of design verification experience 3+ years of experience in ASIC or Silicon Prior experience working with System Verilog Prior experience with ASIC Verification processes, methodologies, flows and tools Experience with scripting languages Python or Perl Preferred Qualifications Understanding of Networking technologies and concepts Experience with Emulation and FPGA Prototyping Experience with Post-silicon lab bring-up Experience with C/C++ Programming Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.